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Mono CODEC with Speaker Driver
DESCRIPTION
The WM8510 is a low power, high quality mono codec designed for Voice over Internet Protocol (VoIP) and Digital Telephones. The device integrates support for one pseudo-differential and one single ended input (Handset Mic and Speaker Mic) and includes drivers for speakers or headset, and mono line output, making it ideal for Telephone designs. External component requirements are reduced as no separate microphone or earpiece amplifiers are required. Advanced Sigma Delta Converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8 to 48kHz. Additional digital filtering options are available in the ADC path, to cater for application filtering such as `wind noise reduction', plus an advanced mixed signal ALC function with noise gate is provided. An on-chip PLL is provided to generate the required Master Clock from an external reference clock. The PLL clock can also be output if required elsewhere in the system. The WM8510 operates at supply voltages from 2.5 to 3.6V, although the digital supplies can operate at voltages down to 1.71V to save power. The speaker and mono outputs use a separate supply of up to 5V which enables increased output power if required. Different sections of the chip can also be powered down under software control by way of the selectable two or three wire control interface. WM8510 is supplied in a convenient 28-lead SSOP package, offering high levels of functionality in an easy to use package. *
WM8510
FEATURES
* * * * * * * * * Mono Codec: Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz DAC SNR 93dB, THD -84dB (`A'-weighted @ 8 - 48kHz) ADC SNR 90dB, THD -80dB (`A'-weighted @ 8 - 48kHz) On-chip Headphone/Speaker Driver with `cap-less' connect - 40mW output power into 16 / 3.3V SPKVDD - BTL speaker drive 0.8W into 8 / 5V SPKVDD Earpiece Line output Multiple analog inputs, plus analog bypass path (0 or -10dB) Mic Preamps: Two Microphone Interfaces - One pseudo-differential input with common mode rejection - One single ended input - Programmable preamp gain - Programmable ALC / Noise Gate in ADC path Low-noise bias supplied for microphone
Other Features * Digital Playback Limiter * Programmable ADC High Pass Filter (wind noise reduction) * Programmable ADC Notch Filter * On-chip PLL * Low power, low voltage - 2.5V to 3.6V (digital supplies: 1.71V to 3.6V) - power consumption <10mW all-on 48kHz mode * 28 lead SSOP package
APPLICATIONS
* * * * * VoIP Telephones Digital Telephones Conference Speaker-phone Mobile Telephone Hands-free Kits General Purpose low power audio CODEC
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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Production Data, December 2006, Rev 4.1 Copyright 2006 Wolfson Microelectronics plc
WM8510 TABLE OF CONTENTS
Production Data
DESCRIPTION .......................................................................................................1 BLOCK DIAGRAM .................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY ............................................................................................................ 8
SIGNAL TIMING REQUIREMENTS .......................................................................9
SYSTEM CLOCK TIMING ............................................................................................. 9 AUDIO INTERFACE TIMING - MASTER MODE .......................................................... 9 AUDIO INTERFACE TIMING - SLAVE MODE............................................................ 10 CONTROL INTERFACE TIMING - 3-WIRE MODE .................................................... 11 CONTROL INTERFACE TIMING - 2-WIRE MODE .................................................... 12
DEVICE DESCRIPTION.......................................................................................13
INTRODUCTION ......................................................................................................... 13 INPUT SIGNAL PATH ................................................................................................. 14 ANALOGUE TO DIGITAL CONVERTER (ADC).......................................................... 19 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 22 OUTPUT SIGNAL PATH ............................................................................................. 35 ANALOGUE OUTPUTS............................................................................................... 40 OUTPUT SWITCH ...................................................................................................... 45 DIGITAL AUDIO INTERFACES................................................................................... 47 AUDIO SAMPLE RATES ............................................................................................. 52 MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ............................................... 53 GENERAL PURPOSE INPUT/OUTPUT...................................................................... 55 CONTROL INTERFACE.............................................................................................. 55 RESETTING THE CHIP .............................................................................................. 56 POWER SUPPLIES .................................................................................................... 57 POWER MANAGEMENT ............................................................................................ 60
REGISTER MAP...................................................................................................63
REGISTER BITS BY ADDRESS ................................................................................. 64
DIGITAL FILTER CHARACTERISTICS ...............................................................75
TERMINOLOGY .......................................................................................................... 75 DAC FILTER RESPONSES......................................................................................... 76 ADC FILTER RESPONSES......................................................................................... 76 DE-EMPHASIS FILTER RESPONSES........................................................................ 77 HIGHPASS FILTER..................................................................................................... 78
APPLICATIONS INFORMATION .........................................................................79
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 79
IMPORTANT NOTICE ..........................................................................................81
ADDRESS ................................................................................................................... 81
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PIN CONFIGURATION
ORDERING INFORMATION
ORDER CODE WM8510GEDS/V WM8510GEDS/RV Note: Reel Quantity = 2,000 TEMPERATURE RANGE -25C to +85C -25C to +85C PACKAGE 28-lead SSOP (Pb-free) 28-lead SSOP (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PACKAGE BODY TEMPERATURE 260oC 260oC
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WM8510 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME VMID MICN MICP MICBIAS NC AVDD AGND AGND DCVDD DBVDD DGND ADCDAT DACDAT FRAME BCLK MCLK CSB/GPIO SCLK SDIN MODE MONOOUT SPKOUTP SPKGND SPKGND SPKOUTN SPKVDD SPKVDD MIC2 TYPE Reference Analog Input Analog Input Analog Output NC Supply Supply Supply Supply Supply Supply Digital Output Digital Input Digital Input/Output Digital Input/Output Digital Input Digital Input/Output Digital Input Digital Input/Output Digital Input Analog Output Analog Output Supply Supply Analog Output Supply Supply Analog Input Microphone negative input Microphone positive input (common mode) Microphone Bias No Connect Analogue supply (feeds ADC, DAC and PLL) Analogue ground (feeds ADC, DAC and PLL) Analogue ground (feeds ADC, DAC and PLL) Digital Core supply Digital Buffer (Input/Output) supply Digital ground ADC Digital Audio Data Output DAC Digital Audio Data Input DAC and ADC Sample Rate Clock or Frame synch Digital Audio Port Clock Master Clock Input DESCRIPTION Decoupling for midrail reference voltage
Production Data
3-Wire MPU Chip Select or General Purpose Input/Output pin. 3-Wire MPU Clock Input / 2-Wire MPU Clock Input 3-Wire MPU Data Input / 2-Wire MPU Data Input/Output Control Interface Mode Selection Pin. Mono Audio Output Speaker Output Positive Speaker ground (feeds speaker and mono output amps only) Speaker ground (feeds speaker and mono output amps only) Speaker Output Negative Speaker supply (feeds speaker and mono output amps only) Speaker supply (feeds speaker and mono output amps only) Second Analog Input
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION DBVDD, DCVDD, AVDD supply voltages SPKVDD supply voltage Voltage range digital inputs Voltage range analogue inputs Operating temperature range, TA Storage temperature after soldering Notes 1. 2. 3. Analogue and digital grounds must always be within 0.3V of each other. All digital and analogue supplies are completely independent from each other. When using the PLL, DCVDD should be 1.9V MIN -0.3V -0.3V DGND -0.3V AGND -0.3V -25C -65C MAX +3.63V +7V DVDD +0.3V AVDD +0.3V +85C +150C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supplies range Speaker supply Ground Notes 1. DCVDD DBVDD at all times. SYMBOL DCVDD DBVDD AVDD SPKVDD DGND,AGND, SPKGND TEST CONDITIONS MIN 1.71 1.71 2.5 2.5 0 TYP MAX 3.6 3.6 3.6 5.5 UNIT V V V V V
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WM8510 ELECTRICAL CHARACTERISTICS
Production Data
Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Microphone Inputs (MICN, MICP) Full-scale Input Signal Level (Note 1) - note this changes with AVDD Mic PGA equivalent input noise Input resistance Input resistance Input resistance Input resistance Input Capacitance Recommended coupling cap Programmable Gain Programmable Gain Step Size Mute Attenuation Selectable Input Gain Boost (0/+20dB) Gain Boost Automatic Level Control (ALC)/Limiter - ADC only Target Record Level Programmable Gain Programmable Gain Step Size Gain Hold Time (Note 2) Gain Ramp-Up (Decay) Time (Note 3) tHOLD tDCY Guaranteed Monotonic MCLK=12.288MHz (Note 4) ALCMODE=0 (ALC), MCLK=12.288MHz (Note 4) ALCMODE=1 (limiter), MCLK=12.288MHz (Note 4) Gain Ramp-Down (Attack) Time (Note 3) tATK ALCMODE=0 (ALC), MCLK=12.288MHz (Note 4) ALCMODE=1 (limiter), MCLK=12.288MHz (Note 4) Analogue to Digital Converter (ADC) Signal to Noise Ratio (Note 5) Total Harmonic Distortion (Note 6) SNR THD A-weighted, 0dB PGA gain -1dBFS input, 0dB PGA gain 87 90 -80 -65 dB dB -28.5 -12 0.75 0, 2.67, 5.33, 10.67, ... , 43691 (time doubles with each step) 3.3, 6.6, 13.1, ... , 3360 (time doubles with each step) 0.73, 1.45, 2.91, ... , 744 (time doubles with each step) 0.83, 1.66, 3.33, ... , 852 (time doubles with each step) 0.18, 0.36, 0.73, ... , 186 (time doubles with each step) ms -6 35.25 dB dB dB ms ms 0 20 dB Guaranteed monotonic VINFS PGABOOST = 0dB INPPGAVOL = 0dB 1.0 0 150 Gain set to 35.25dB Gain set to 0dB Gain set to -12dB MICP2INPPGA = 1 1.6 47 75 94 10 220 -12 0.75 108 35.25 Vrms dBV uV k k k k pF pF dB dB dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
At 35.25dB gain RMICIN RMICIN RMICIN RMICIP CMICIN CCOUP
MIC Input Programmable Gain Amplifier (PGA)
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Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER MIC2 Analogue Input Full-scale Input Signal Level (0dB) - note this scales with AVDD Input Resistance Input Capacitance Signal to Noise Ratio (Note 5) Total Harmonic Distortion (Note 6) 0dB Full Scale output voltage (Note 7) Speaker Output PGA Programmable Gain Programmable Gain Step Size Output Power Total Harmonic Distortion PO THD Guaranteed monotonic BTL Speaker Output (SPKOUTP, SPKOUTN with 8 bridge tied load) Output power is very closely correlated with THD; see below PO =180mW, RL = 8, SPKVDD=3.3V PO =400mW, RL = 8, SPKVDD=3.3V PO =360mW, RL = 8, SPKVDD=5V PO =800mW, RL = 8, SPKVDD=5V Signal to Noise Ratio SNR SPKVDD=3.3V, RL = 8 SPKVDD=5V, RL = 8 Power Supply Rejection Ratio `Headphone' output (SPKOUTP, SPKOUTN with resistive load to ground) Signal to Noise Ratio Total Harmonic Distortion SNR THD Po=20mW, RL = 16, SPKVDD=3.3V Po=20mW, RL = 32, SPKVDD=3.3V Microphone Bias Bias Voltage (MBVSEL=0) Bias Voltage (MBVSEL=1) Bias Current Source Output Noise Voltage Digital Input / Output Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level VIH VIL VOH VOL IOL=1mA IOH-1mA 0.9xDVDD 0.1xDVDD 0.7xDVDD 0.3xDVDD V V V V VMICBIAS VMICBIAS IMICBIAS Vn 1kHz to 20kHz 15 0.9*AVDD 0.65*AVDD 3 V V mA nV/Hz 93 0.02 -74 0.017 - 75 dB % dB % dB 0.03 -70 5.0 -26 0.02 -75 0.06 -65 90 90 50 % dB % dB % dB % dB dB dB dB -57 1 6 dB dB VINFS 1.0 0 MIC2MODE=0 20 10 A-weighted RL = 10 k full-scale signal MONOBOOST=0 MONOBOOST=1 90 93 -84 AVDD/3.3 1.5x (AVDD/3.3) -70 Vrms dBV k pF dB dB VRMS SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
RMIC2IN CMIC2IN SNR THD
Digital to Analogue Converter (DAC) to MONO output (all data measured with 10k / 50pF load)
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TERMINOLOGY
1. 2. 3. 4. 5. 6. 7.
Production Data
MICN input only in single ended microphone configuration. Maximum input signal to MICP without distortion is -3dBV. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It does not apply to ramping down the gain when the signal is too loud, which happens without a delay. Ramp-up and Ramp-Down times are defined as the time it takes the PGA to change its gain by 6dB. All hold, ramp-up and ramp-down times scale proportionally with MCLK Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). THD (dB) - THD is a ratio, of the rms values, of Noise Signal. The maximum output voltage can be limited by the speaker power supply. If MONOBOOST=1 then SPKVDD should be 1.5xAVDD or higher to prevent clipping taking place in the output stage.
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SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
Figure 1 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC, Slave Mode PARAMETER System Clock Timing Information MCLK System clock cycle time MCLK duty cycle TMCLKY TMCLKDS Tbd 60:40 40:60 ns SYMBOL MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - MASTER MODE
Figure 2 Digital Audio Data Timing - Master Mode (see Control Interface)
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Test Conditions
Production Data
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information FRAME propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT hold time from BCLK rising edge tDL tDDA tDST tDHT 10 10 10 10 ns ns ns ns SYMBOL MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - SLAVE MODE
Figure 3 Digital Audio Data Timing - Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK cycle time BCLK pulse width high BCLK pulse width low FRAME set-up time to BCLK rising edge FRAME hold time from BCLK rising edge DACDAT hold time from BCLK rising edge DACDAT set-up time to BCLK rising edge ADCDAT propagation delay from BCLK falling edge Note: BCLK period should always be greater than or equal to MCLK period. tBCY tBCH tBCL tLRSU tLRH tDH tDS tDD 50 20 20 10 10 10 10 20 ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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CONTROL INTERFACE TIMING - 3-WIRE MODE
Figure 4 Control Interface Timing - 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising Pulse width of spikes that will be suppressed tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tps 80 200 80 80 40 40 40 40 40 0 5 ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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CONTROL INTERFACE TIMING - 2-WIRE MODE
t3 SDIN t4 t6 SCLK t1 t9 t7 t2 t8 t5 t3
Production Data
Figure 5 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 0 1.3 600 600 600 100 300 300 526 kHz us ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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DEVICE DESCRIPTION
INTRODUCTION
The WM8510 is a low power audio codec combining a high quality mono audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device are anticipated to include VoIP telephones, digital telephones, conference speaker phones and mobile hands-free kits.
FEATURES
The chip offers great flexibility in use, and so can support many different modes of operation as follows:
MICROPHONE INPUTS
Two microphone inputs are provided, allowing for either a differential microphone input or a single ended microphone to be connected. These inputs have a user programmable gain range of -12dB to +35.25dB using internal resistors. After the input PGA stage comes a boost stage which can add a further 20dB of gain. A microphone bias is output from the chip which can be used to bias the microphones. The signal routing can be configured to allow manual adjustment of mic levels, or to allow the ALC loop to control the level of mic signal that is transmitted. Total gain through the microphone paths of up to +55.25dB can be selected.
FLEXIBLE MIC2 INPUT
The flexible configuration of the mono input, MIC2, with integrated on-chip resistors allows several analogue signals to be summed into the single input if required. This can be used as a microphone, line input or an input for warning tones (beep) etc. The output from this circuit can be summed into the mono output and/or the speaker output paths, so allowing for mixing of audio with `backing music' etc as required.
SIDETONE ATTENUATION
A bypass path allows analog signals to travel directly to the outputs without passing through the ADC and DAC. For side tone features in telephone handsets this analogue bypass can be attenuated.
PGA AND ALC OPERATION
A programmable gain amplifier is provided in the input path to the ADC. This may be used manually or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the recording volume constant.
ADC
The mono ADC uses a multi-bit high-order oversampling architecture to deliver optimum performance with low power consumption. Various sample rates are supported, from the 8ks/s rate typically used in voice dictation, up to the 48ks/s rate used in high quality audio applications.
HI-FI DAC
The hi-fi DAC provides high quality audio playback suitable for all portable mono audio type applications.
DIGITAL FILTERING
Advanced Sigma Delta Converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8ks/s to 48ks/s. Application specific digital filters are also available which help to reduce the effect of specific noise sources such as `wind noise'. The filters include a programmable ADC high pass filter and a programmable ADC notch filter.
OUTPUT MIXING AND VOLUME ADJUST
Flexible mixing is provided on the outputs of the device; a mixer is provided for the speaker outputs, and an additional mono summer for the mono output. These mixers allow the output of the DAC, the output of the ADC volume control and the MIC2 input to be combined. The output volume can be adjusted using the integrated digital volume control and there is additional analogue gain adjustment capability on the speaker output.
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AUDIO INTERFACES
Production Data
The WM8510 has a standard audio interface, to support the transmission of audio data to and from the chip. This interface is a 4 wire standard audio interface which supports a number of audio data formats including I2S, DSP Mode, MSB-First, left justified and MSB-First, right justified, and can operate in master or slave modes.
CONTROL INTERFACES
To allow full software control over all its features, the WM8510 offers a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. The selection between 2-wire mode and 3-wire mode is determined by the state of the MODE pin. If MODE is high then 3-wire control mode is selected, if MODE is low then 2-wire control mode is selected. In 2 wire mode, only slave operation is supported, and the address of the device is fixed as 0011010.
CLOCKING SCHEMES
WM8510 offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to the DAC/ADC. However, a PLL is also included which may be used to generate the internal master clock frequency in the event that this is not available from the system controller. This PLL uses an input clock, typically the 12MHz USB or ilink clock, to generate high quality audio clocks. If this PLL is not required for generation of these clocks, it can be reconfigured to generate alternative clocks which may then be output on the CSB/GPIO pin and used elsewhere in the system.
POWER CONTROL
The design of the WM8510 has given much attention to power consumption without compromising performance. It operates at low supply voltages, and includes the facility to power off any unused parts of the circuitry under software control, includes standby and power off modes.
INPUT SIGNAL PATH
The WM8510 has 3 flexible analogue inputs for two separate microphone inputs. These inputs can be used in a variety of ways. The input signal path before the ADC has a flexible PGA block which then feeds into a gain boost/mixer stage.
MICROPHONE INPUTS
The WM8510 can accommodate a variety of microphone configurations including single ended and pseudo-differential inputs. The inputs through the MICN, MICP and optionally MIC2 pins are amplified through the input PGA as shown in Figure 6. A pseudo differential input is the preferential configuration where the positive terminal of the input PGA is connected to the MICP input pin by setting MICP2INPPGA=1. The microphone ground should then be connected to MICN (when MICN2INPPGA=1) or optionally to MIC2 (when MIC2_2INPPGA=1) input pins. Alternatively a single ended microphone can be connected to the MICN input with MICN2INPPGA set to 1. The non-inverting terminal of the input PGA should be connected internally to VMID by setting MICP2INPPGA to 0.
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Figure 6 Microphone Input PGA Circuit (switch positions shown are for pseudo-differential mic input)
REGISTER ADDRESS R44 Input Control
BIT 0
LABEL MICP2INPPGA
DEFAULT 1
DESCRIPTION Connect input PGA amplifier positive terminal to MICP or VMID. 0 = input PGA amplifier positive terminal connected to VMID 1 = input PGA amplifier positive terminal connected to MICP through variable resistor string Connect MICN to input PGA negative terminal. 0=MICN not connected to input PGA 1=MICN connected to input PGA amplifier negative terminal. Select MIC2 amplifier output as input PGA signal source. 0=MIC2 not connected to input PGA 1=MIC2 connected to input PGA amplifier negative terminal.
1
MICN2INPPGA
1
2
MIC2_2INPPGA
0
The input PGA is enabled by the INPGAEN register bit. REGISTER ADDRESS R2 Power Management 2 2 BIT LABEL INPGAEN DEFAULT 0 DESCRIPTION Input microphone PGA enable 0 = disabled 1 = enabled
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INPUT PGA VOLUME CONTROL
Production Data
The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the MICN input to the PGA output and from the MIC2 amplifier to the PGA output are always common and controlled by the register bits INPPGAVOL[5:0]. These register bits also affect the MICP pin when MICP2INPPGA=1. When the Automatic Level Control (ALC) is enabled the input PGA gain is then controlled automatically and the INPPGAVOL bits should not be used. REGISTER ADDRESS R45 Input PGA volume control BIT 5:0 LABEL INPPGAVOL DEFAULT 010000 DESCRIPTION Input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = +35.25dB Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. ALC function select: 0=ALC off (PGA gain set by INPPGAVOL register bits) 1=ALC on (ALC controls PGA gain)
6
INPPGAMUTE
0
7
INPPGAZC
0
R32 ALC control 1
8
ALCSEL
0
Table 1 Input PGA Volume Control
MIC 2 INPUT
A second mic input circuit, MIC2 (Figure 7) is provided which consists of an amplifier which can be configured either as an inverting buffer for a single input signal or as a mixer/summer for multiple inputs with the use of external resistors. The circuit is enabled by the register bit MIC2EN.
Figure 7 MIC2 Input Circuit The MIC2MODE register bit controls the input mode of operation: In buffer mode (MIC2MODE=0) the switch labelled MIC2SW in Figure 7 is open and the signal at the MIC2 pin will be buffered and inverted through the MIC2 circuit using only the internal components.
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In mixer mode (MIC2MODE=1) the on-chip input resistor is bypassed, this allows the user to sum in multiple inputs with the use of external resistors. When used in this mode there will be gain variations through this path from part to part due to the variation of the internal 20k resistors relative to the higher tolerance external resistors. REGISTER ADDRESS R1 Power management 1 R44 Input control BIT 6 LABEL MIC2EN DEFAULT 0 DESCRIPTION MIC2 input buffer enable 0 = OFF 1 = ON 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed)
3
MIC2MODE
0
Table 2 MIC2 Input Buffer Control
INPUT BOOST
The input BOOST circuit has 3 selectable inputs: the input microphone PGA output, the MIC2 amplifier output and the MICP input pin (when not using a differential microphone configuration). These three inputs can be mixed together and have individual gain boost/adjust as shown in Figure 8.
Figure 8 Input Boost Stage The input PGA path can have a +20dB boost (PGABOOST=1) a 0dB pass through (PGABOOST=0) or be completely isolated from the input boost circuit (INPPGAMUTE=1). REGISTER ADDRESS R45 Input PGA gain control BIT 6 LABEL INPPGAMUTE DEFAULT 0 DESCRIPTION Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage.
R47 Input BOOST control
8
PGABOOST
1
Table 3 Input BOOST Stage Control The MIC2 amplifier path to the BOOST stage is controlled by the MIC2_2BOOSTVOL[2:0] register bits. When MIC2_2BOOSTVOL=000 this path is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB.
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Production Data The MICP path to the BOOST stage is controlled by the MICP2BOOSTVOL[2:0] register bits. When MICP2BOOSTVOL=000 this input pin is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. REGISTER ADDRESS R47 Input BOOST control BIT 2:0 LABEL MIC2_2BOOSTV OL DEFAULT 000 DESCRIPTION Controls the MIC2 amplifier to the input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Controls the MICP pin to the input boost stage (NB, when using this path set MICPZIUNPPGA=0): 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage
6:4
MICP2BOOSTVOL
000
Table 4 Input BOOST Stage Control The BOOST stage is enabled under control of the BOOSTEN register bit. REGISTER ADDRESS R2 Power management 2 BIT 4 LABEL BOOSTEN DEFAULT 0 DESCRIPTION Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON
Table 5 Input BOOST Enable Control
MICROPHONE BIASING CIRCUIT
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via the MBVSEL register bit. When MBVSEL=0, MICBIAS=0.9*AVDD and when MBVSEL=1, MICBIAS=0.75*AVDD. The output can be enabled or disabled using the MICBEN control bit. REGISTER ADDRESS R1 Power management 1 BIT 4 LABEL MICBEN DEFAULT 0 DESCRIPTION Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON
Table 6 Microphone Bias Enable REGISTER ADDRESS R44 Input Control BIT 8 LABEL MBVSEL DEFAULT 0 DESCRIPTION Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD
Table 7 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 9. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA.
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MBVSEL=0 MICBIAS = 1.8 x VMID = 0.9 X AVDD MBVSEL=1 MICBIAS = 1.3 x VMID = 0.65 X AVDD
VMID internal resistor
MB
internal resistor
AGND
Figure 9 Microphone Bias Schematic
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8510 uses a multi-bit, oversampled sigma-delta ADC channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0Vrms. Any voltage greater than full scale may overload the ADC and cause distortion.
ADC DIGITAL FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital filter path is illustrated in Figure 10.
Figure 10 ADC Digital Filter Path
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The ADC is enabled by the ADCEN register bit. REGISTER ADDRESS R2 Power management 2 Table 8 ADC Enable BIT 0 LABEL ADCEN DEFAULT 0
Production Data
DESCRIPTION 0 = ADC disabled 1 = ADC enabled
The polarity of the output signal can also be changed under software control using the ADCPOL register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate is 128x which gives best performance. REGISTER ADDRESS R14 ADC Control BIT 3 LABEL ADCOSR DEFAULT 0 DESCRIPTION ADC oversample rate select: 0=64x (lower power) 1=128x (best performance) 0=normal 1=inverted
0
ADCPOL
0
Table 9 ADC Oversample Rate Select
SELECTABLE HIGH PASS FILTER
A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown in Table 11 REGISTER ADDRESS R14 ADC Control 8 BIT LABEL HPFEN DEFAULT 1 DESCRIPTION High Pass Filter Enable 0=disabled 1=enabled Select audio mode or application mode 0=Audio mode (1st order, fc = ~3.7Hz) nd 1=Application mode (2 order, fc = HPFCUT) Application mode cut-off frequency See Table 11 for details.
7
HPFAPP
0
6:4 Table 10 ADC Filter Select HPFCUT
HPFCUT
000
FS (KHZ) SR=101/100 8 11.025 113 141 180 225 281 360 450 563 12 122 153 156 245 306 392 490 612 16 82 102 131 163 204 261 327 408 SR=011/010 22.05 113 141 180 225 281 360 450 563 24 122 153 156 245 306 392 490 612 32 82 102 131 163 204 261 327 408 SR=001/000 44.1 113 141 180 225 281 360 450 563 48 122 153 156 245 306 392 490 612
000 001 010 011 100 101 110 111
82 102 131 163 204 261 327 408
Table 11 High Pass Filter Cut-off Frequencies (HPFAPP=1) Note that the High Pass filter values (when HPFAPP=1) work on the basis that the SR register bits are set correctly for the actual sample rate as shown in Table 11.
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PROGRAMMABLE NOTCH FILTER
A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup.
REGISTER ADDRESS R27 Notch Filter 1
BIT 6:0 7
LABEL NFA0[13:7] NFEN
DEFAULT 0 0
DESCRIPTION Notch Filter a0 coefficient, bits [13:7] Notch filter enable: 0=Disabled 1=Enabled Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch Filter a0 coefficient, bits [6:0] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch Filter a1 coefficient, bits [13:7] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch Filter a1 coefficient, bits [6:0] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high.
8
NFU
0
R28 Notch Filter 2
6:0 8
NFA0[6:0] NFU]
0 0
R29 Notch Filter 3
6:0 8
NFA1[13:7] NFU
0 0
R30 Notch Filter 4
6:0 8
NFA1[6:0] NFU
0 0
Table 12 Notch Filter Function The coefficients are calculated as follows:
a0 =
1 - tan( wb / 2) 1 + tan( wb / 2)
a1 = -(1 + a0 ) cos(w0 )
Where:
w0 = 2f c / f s wb = 2f b / f s
fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz The actual register values can be determined from the coefficients as follows: NFA0 = -a0 x 213 NFA1 = -a1 x 212
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DIGITAL ADC VOLUME CONTROL
Production Data
The output of the ADCs can be digitally attenuated over a range from -127dB to 0dB in 0.5dB steps. The gain for a given eight-bit code X is given by: Gain = 0.5 x (x-255) dB for 1 x 255, MUTE for x = 0 REGISTER ADDRESS R15 ADC Digital Volume BIT 7:0 LABEL ADCVOL [7:0] DEFAULT 11111111 ( 0dB ) DESCRIPTION ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB
Table 13 ADC Volume
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)
The WM8510 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment of the input PGA in response to the amplitude of the input signal. A digital peak detector monitors the input signal amplitude and compares it to a register defined threshold level (ALCLVL). If the signal is below the threshold, the ALC will increase the gain of the PGA at a rate set by ALCDCY. If the signal is above the threshold, the ALC will reduce the gain of the PGA at a rate set by ALCATK. The ALC has two modes selected by the ALCMODE register: normal mode and peak limiter mode. The ALC/limiter function is enabled by setting the register bit R32[8] ALCSEL.
REGISTER ADDRESS R32 (20h) ALC Control 1
BIT 2:0
LABEL ALCMIN [2:0]
DEFAULT 000 (-12dB)
DESCRIPTION Set minimum gain of PGA 000 = -12dB 001 = -6dB 010 = 0dB 011 = +6dB 100 = +12dB 101 = +18dB 110 = +24dB 111 = +30dB Set Maximum Gain of PGA 111 = +35.25dB 110 = +29.25dB 101 = +23.25dB 100 = +17.25dB 011 = +11.25dB 010 = +5.25dB 001 = -0.75dB 000 = -6.75dB ALC function select 0 = ALC disabled 1 = ALC enabled
5:3
ALCMAX [2:0]
111 (+35.25dB)
8
ALCSEL
0
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WM8510
ALC target - sets signal level at ADC input 1111 = -6dBFS 1110 = -7.5dBFS 1101 = -9dBFS 1100 = -10.5dBFS 1011 = -12dBFS 1010 = -13.5dBFS 1001 = -15dBFS 1000 = -16.5dBFS 0111 = -18dBFS 0110 = -19.5dBFS 0101 = -21dBFS 0100 = -22.5dBFS 0011 = -24dBFS 0010 = -25.5dBFS 0001 = -27dBFS 0000 = -28.5dBFS ALC uses zero cross detection circuit. 0 = Disabled (recommended) 1 = Enabled It is recommended that zero cross is not used in conjunction with the ALC or Limiter functions ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms 0011 = 10.66ms 0100 = 21.32ms 0101 = 42.64ms 0110 = 85.28ms 0111 = 0.17s 1000 = 0.34s 1001 = 0.68s 1010 or higher = 1.36s
8
ALCZC
0 (zero cross off)
7:4
ALCHLD [3:0]
0000 (0ms)
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REGISTER ADDRESS R34 (22h) ALC Control 3 BIT 8 LABEL ALCMODE DEFAULT 0
Production Data DESCRIPTION Determines the ALC mode of operation: 0 = ALC mode (Normal Operation) 1 = Limiter mode. Decay (gain ramp-up) time (ALCMODE ==0) Per step 0000 0001 0010 1010 or higher 0011 (5.8ms/6dB) 410us 820us 1.64ms 420ms Per 6dB 3.38ms 6.56ms 13.1ms 3.36s 90% of range 23.6ms 47.2ms 94.5ms 24.2s
7:4
ALCDCY [3:0]
0011 (26ms/6dB)
... (time doubles with every step)
Decay (gain ramp-up) time (ALCMODE ==1) Per step 0000 0001 0010 1010 90.8us 182us 363us 93ms Per 6dB 726us 1.45ms 2.91ms 744ms 90% of range 5.23ms 10.5ms 20.9ms 5.36s
... (time doubles with every step) 3:0 ALCATK [3:0] 0010 (3.3ms/6dB) ALC attack (gain ramp-down) time (ALCMODE == 0) Per step 0000 0001 0010 1010 or higher 0010 (726us/6dB) 104us 208us 416us 106ms Per 6dB 832us 1.66ms 3.33ms 852ms 90% of range 6ms 12ms 24ms 6.13s
... (time doubles with every step)
ALC attack (gain ramp-down) time (ALCMODE == 1) Per step 0000 0001 0010 1010 or higher 22.7us 45.4us 90.8us 23.2ms Per 6dB 182.4us 363us 726us 186ms 90% of range 1.31ms 2.62ms 5.23ms 1.34s
... (time doubles with every step)
Table 14 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits.
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NORMAL MODE
In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing the gain of the PGA. The following diagram shows an example of this.
Figure 11 ALC Normal Mode Operation
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LIMITER MODE
Production Data
In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is enabled in limiter mode. If the ALC is started in limiter mode, this is the gain setting of the PGA at start-up. If the ALC is switched into limiter mode after running in ALC mode, the starting gain will be the gain at switchover. The diagram below shows an example of limiter mode.
Figure 12 ALC Limiter Mode Operation
ATTACK AND DECAY TIMES
The attack and decay times set the update times for the PGA gain. The attack time is the time constant used when the gain is reducing. The decay time is the time constant used when the gain is increasing. In limiter mode, the time constants are faster than in ALC mode. The time constants are shown below in terms of a single gain step, a change of 6dB and a change of 90% of the PGAs gain range. Note that, these times will vary slightly depending on the sample rate used (specified by the SR register).
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NORMAL MODE
ALCMODE = 0 (Normal Mode) Attack Time (s) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 t ATK 104s 208s 416s 832s 1.66ms 3.33ms 6.66ms 13.3ms 26.6ms 53.2ms 106ms t ATK6dB 832s 1.66ms 3.33ms 6.66ms 13.3ms 26.6ms 53.2ms 106ms 213.2ms 426ms 852ms
Decay Time (s) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 t DCY 410s 820s 1.64ms 3.28ms 6.56ms 13.1ms 26.2ms 52.5ms 105ms 210ms 420ms t DCY 6dB 3.28ms 6.56ms 13.1ms 26.2ms 52.5ms 105ms 210ms 420ms 840ms 1.68s 3.36s t DCY 90% 23.6ms 47.2ms 94.5ms 189ms 378ms 756ms 1.51s 3.02s 6.05s 12.1s 24.2s
t ATK90% 6ms 12ms 24ms 48ms 96ms 192ms 384ms 767ms 1.53s 3.07s 6.13s
ALCMODE = 0 (Normal Mode)
Table 15 ALC Normal Mode (Attack and Decay times)
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LIMITER MODE
Production Data
ALCMODE = 1 (Limiter Mode) Attack Time (s) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 t ATKLIM 22.7s 45.4S 90.8S 182S 363S 726S 1.45ms 2.9ms 5.81ms 11.6ms 23.2ms t ATKLIM6dB 182s 363s 726s 1.45ms 2.91ms 5.81ms 11.6ms 23.2ms 46.5ms 93ms 186ms t ATKLIM90% 1.31ms 2.62ms 5.23ms 10.5ms 20.9ms 41.8ms 83.7ms 167ms 335ms 669ms 1.34s
ALCMODE = 1 (Limiter Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 t DCY LIM 90.8s 182S 363S 726S 1.45ms 2.91ms 5.81ms 11.6ms 23.2ms 46.5ms 93ms Attack Time (s) t DCY LIM6dB t DCY LIM90% 726s 5.23ms 1.45ms 10.5ms 2.91ms 20.9ms 5.81ms 41.8ms 11.6ms 83.7ms 23.2ms 167ms 46.5ms 335ms 93ms 669ms 186ms 1.34s 372ms 2.68s 744ms 5.36s
Table 16 ALC Limiter Mode (Attack and Decay times)
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MINIMUM AND MAXIMUM GAIN
The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.
REGISTER ADDRESS R32 ALC Control 1
BIT 5:3 2:0
LABEL ALCMAX ALCMIN
DEFAULT 111 000
DESCRIPTION Set Maximum Gain of PGA Set minimum gain of PGA
Table 17 ALC Max/Min Gain
In normal mode, ALCMAX sets the maximum boost which can be applied to the signal. In limiter mode, ALCMAX will normally have no effect (assuming the starting gain value is less than the maximum gain specified by ALCMAX) because the maximum gain is set at the starting gain level. ALCMIN sets the minimum gain value which can be applied to the signal.
Figure 13 ALC Min/Max Gain
ALCMAX 111 110 101 100 011 010 001 000
Maximum Gain (dB) 35.25 29.25 23.25 17.25 11.25 5.25 -0.75 -6.75
Table 18 ALC Max Gain Values
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ALCMIN 000 001 010 011 100 101 110 111 Minimum Gain (dB) -12 -6 0 6 12 18 24 30
Production Data
Table 19 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or changing the ALCMAX or ALCMIN settings during operation, the ALC will immediately adjust the gain to return to the ALC operating range. It is recommended that the ALC starting gain is set between the ALCMAX and ALCMIN limits.
ALC HOLD TIME (NORMAL MODE ONLY)
In Normal mode, the ALC has an adjustable hold time which sets a time delay before the ALC begins its decay phase (gain increasing). The hold time is set by the ALCHLD register.
REGISTER ADDRESS R33 ALC Control 2
BIT 7:4
LABEL ALCHLD
DEFAULT 0000
DESCRIPTION ALC hold time before gain is increased.
Table 20 ALC Hold Time If the hold time is exceeded this indicates that the signal has reached a new average level and the ALC will increase the gain to adjust for that new average level. If the signal goes above the threshold during the hold period, the hold phase is abandoned and the ALC returns to normal operation.
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Figure 14 ALCLVL
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Production Data
Input Signal
tHOLD
PGA Gain
Output of PGA
ALCLVL
Figure 15 ALC Hold Time
ALCHLD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
t HOLD (s) 0 2.67ms 5.34ms 10.7ms 21.4ms 42.7ms 85.4ms 171ms 342ms 684ms 1.37s
Table 21 ALC Hold Time Values
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PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (-1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. Note: If ALCATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used.
NOISE GATE (NORMAL MODE ONLY)
When the signal is very quiet and consists mainly of noise, the ALC function may cause "noise pumping", i.e. loud hissing noise during silence periods. The WM8510 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH. The noise gate cuts in when: Signal level at ADC [dBFS] < NGTH [dBFS] + PGA gain [dB] + Mic Boost gain [dB]
This is equivalent to: Signal level at input pin [dBFS] < NGTH [dBFS] The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set-up of the function. The noise gate only operates in conjunction with the ALC and cannot be used in limiter mode. REGISTER ADDRESS R35 (23h) ALC Noise Gate Control BIT 2:0 LABEL NGTH DEFAULT 000 DESCRIPTION Noise gate threshold: 000 = -39dB 001 = -45dB 010 = -51db 011 = -57dB 100 = -63dB 101 = -69dB 110 = -75dB 111 = -81dB Noise gate function enable 1 = enable 0 = disable
3
NGATEN
0
Table 22 ALC Noise Gate Control
The diagrams below show the response of the system to the same signal with and without noise gate.
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Figure 16 ALC Operation Above Noise Gate Threshold
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Figure 17 Noise Gate Operation
OUTPUT SIGNAL PATH
The WM8510 output signal paths consist of digital application filters, up-sampling filters, a Hi-Fi DAC, analogue mixers, speaker and mono output drivers. The digital filters and DAC are enabled by bit DACEN. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8510, irrespective of whether the DACs are running or not. The WM8510 DAC receives digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: * * * Digital volume control A digital peak limiter Sigma-Delta Modulation
The high performance sigma-delta audio DAC converts the digital data into an analogue signal.
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Production Data
Figure 18 DAC Digital Filter Path The analogue output from the DAC can then be mixed with the MIC2 analogue input and the ADC analogue input. The mix is fed to the output drivers, SPKOUTP/N, and MONOOUT. MONOOUT: can drive a 16 or 32 headphone or line output or can be a buffered version of VMID (When MONOMUTE=1). SPKOUTP/N: can drive a 16 or 32 stereo headphone or stereo line output, or an 8 BTL mono speaker.
DIGITAL HI-FI DAC VOLUME CONTROL
The signal volume from each Hi-Fi DAC can be controlled digitally. The gain and attenuation range is -127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by: 0.5 x (X-255) dB for 1 X 255; REGISTER ADDRESS R11 DAC Digital Volume BIT 7:0 LABEL DACVOL [7:0] MUTE for X = 0 DEFAULT 11111111 ( 0dB ) DESCRIPTION DAC Digital Volume Control 0000 0000 = Unused 0000 0001 = -127dB = mute 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB
Table 23 DAC Volume
HI-FI DIGITAL TO ANALOGUE CONVERTER (DAC)
Digital `de-emphasis' can be applied to the audio data if necessary. De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. REGISTER ADDRESS R10 DAC Control BIT 5:4 LABEL DEEMPH DEFAULT 00 DESCRIPTION De-Emphasis Control 00 = No de-emphasis 01 = 32kHz sample rate 10 = 44.1kHz sample rate 11 = 48kHz sample rate
Table 24 De-Emphasis
The DAC is enabled by the DACEN register bit. REGISTER ADDRESS R3 Power Management 3 Table 25 DAC Enable BIT 0 LABEL DACEN DEFAULT 0 DESCRIPTION DAC enable 0 = DAC disabled 1 = DAC enabled
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The WM8510 also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will ramp back up to the digital gain setting. This function is enabled by default. To play back an audio signal, it must first be disabled by setting the DACMU bit to zero. REGISTER ADDRESS R10 DAC Control BIT 6 LABEL DACMU DEFAULT 0 DESCRIPTION DAC soft mute enable 0 = DACMU disabled 1 = DACMU enabled
Table 26 DAC Control Register The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters a multi-bit, sigma-delta DAC, which converts it to a high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. The DAC output defaults to non-inverted. Setting DACPOL will invert the DAC output phase.
AUTOMUTE
The DAC has an automute function which applies an analogue mute when 1024 consecutive zeros are detected. The mute is release as soon as a non-zero sample is detected. Automute can be disabled using the AMUTE control bit. REGISTER ADDRESS R10 DAC Control BIT 2 LABEL AMUTE DEFAULT 0 DESCRIPTION DAC auto mute enable 0 = auto mute disabled 1 = auto mute enabled
Table 27 DAC Auto Mute Control Register
DAC OUTPUT LIMITER
The WM8510 has a digital output limiter function. The operation of this is shown in Figure 19. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic.
Figure 19 DAC Digital Limiter Operation
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Production Data The limiter has a programmable upper threshold which is close to 0dB. Referring to Table 30, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. Signals above the upper threshold are attenuated at a specific attack rate (set by the LIMATK register bits) until the signal falls below the threshold. The limiter also has a lower threshold 1dB below the upper threshold. When the signal falls below the lower threshold the signal is amplified at a specific decay rate (controlled by LIMDCY register bits) until a gain of 0dB is reached. Both threshold levels are controlled by the LIMLVL register bits. The upper threshold is 0.5dB above the value programmed by LIMLVL and the lower threshold is 0.5dB below the LIMLVL value. VOLUME BOOST The limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. This operates as an ALC function with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the LIMBOOST register bits. The output limiter volume boost can also be used as a stand alone digital gain boost when the limiter is disabled.
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REGISTER ADDRESS R24 DAC digital limiter control 1 BIT 3:0 LABEL LIMATK DEFAULT 0010 DESCRIPTION Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s Enable the DAC digital limiter: 0=disabled 1=enabled Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000=0dB 0001=+1dB 0010=+2dB ... (1dB steps) 1011=+11dB 1100=+12dB 1101 to 1111=reserved Programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB
7:4
LIMDCY
0011
8
LIMEN
0
R25 DAC digital limiter control 2
3:0
LIMBOOST
0000
6:4
LIMLVL
000
Table 28 DAC Digital Limiter Control
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ANALOGUE OUTPUTS
Production Data
The WM8510 has a single MONO output and two outputs SPKOUTP and SPOUTN for driving a mono BTL speaker. These analogue output stages are supplied from SPKVDD and are capable of driving up to 1.5V rms signals (equivalent to 3V rms into a bridge tied speaker) as shown in Figure 20.
Figure 20 Speaker and Mono Analogue Outputs The Mono and speaker outputs have output driving stages which can be controlled by the register bits MONOBOOST and SPKBOOST respectively. Each output stage has a selectable gain boost of 1.5x. When this boost is enabled the output DC level is also level shifted (from AVDD/2 to 1.5xAVDD/2) to prevent the signal from clipping. A dedicated amplifier, as shown in Figure 20, is used to perform the DC level shift operation. This buffer must be enabled using the BUFDCOPEN register bit for this operating mode. It should also be noted that if SPKVDD is not equal to or greater than 1.5xAVDD this boost mode may result in signals clipping. Table 30 summarises the effect of the SPKBOOST/MONOBOOST control bits.
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REGISTER ADDRESS R49 Output control BIT 2 LABEL SPKBOOST DEFAULT 0 DESCRIPTION Speaker output boost stage control (see Table 30 for details) 0=No boost (outputs are inverting buffers) 1 = 1.5x gain boost Mono output boost stage control (see Table 30 for details) 0=No boost (output is inverting buffer) 1=1.5x gain boost Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. 0=Buffer disabled 1=Buffer enabled (required for 1.5x gain boost)
3
MONOBOOST
0
R1 Power management 1
8
BUFDCOPEN
0
Table 29 Output Boost Control SPKBOOST/ MONOBOOST 0 1 OUTPUT STAGE GAIN 1x 1.5x OUTPUT DC LEVEL AVDD/2 1.5xAVDD/2 OUTPUT STAGE CONFIGURATION Inverting Non-inverting
Table 30 Output Boost Stage Details
SPKOUTP/SPKOUTN OUTPUTS
The SPKOUT pins can drive a single bridge tied 8 speaker or two headphone loads of 16 or 32 or a line output (see Headphone Output and Line Output sections, respectively). The signal to be output on SKPKOUT comes from the Speaker Mixer circuit and can be any combination of the DAC output, the Bypass path (output of the boost stage) and the MIC2 input. The Bypass path has the option of 0dB or -10dB attenuation, selected by the SPKATTN register bit. The SPKOUTP/N volume is controlled by the SPKVOL register bits. Note that gains over 0dB may cause clipping if the signal is large. The SPKMUTE register bit causes the speaker outputs to be muted (the output DC level is driven out). The output pins remains at the same DC level (VMIDOP), so that no click noise is produced when muting or un-muting. The SPKOUTN pin always drives out an inverted version of the SPKOUTP signal. REGISTER ADDRESS R50 Speaker mixer control BIT 0 LABEL DAC2SPK DEFAULT 1 DESCRIPTION Output of DAC to speaker mixer input 0 = not selected 1 = selected Bypass path (output of input boost stage) to speaker mixer input 0 = not selected 1 = selected Output of MIC2 amplifier to speaker mixer input 0 = not selected 1 = selected Attenuation control for bypass path (output of input boost stage) to speaker mixer input 0 = 0dB 1 = -10dB
1
BYP2SPK
0
5
MIC2_2SPK
0
R40 Bypass path attenuation control
1
SPKATTN
0
Table 31 Speaker Mixer Control
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REGISTER ADDRESS R54 Speaker volume control BIT 7 LABEL SPKZC DEFAULT 0
Production Data DESCRIPTION Speaker Volume control enable: 1 = Change gain on zero cross only 0 = Change gain immediately Speaker output mute enable 0=Speaker output enabled 1=Speaker output muted (VMIDOP) Speaker Volume Adjust 111111 = +6dB 111110 = +5dB ... (1.0 dB steps) 111001=0dB ... 000000=-57dB
6
SPKMUTE
0
5:0
SPKVOL [5:0]
111001 (0dB)
Table 32 SPKOUT Volume Control
ZERO CROSS TIMEOUT
A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This is enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital and is equal to 221 * input clock period.
REGISTER ADDRESS R7 Additional control
BIT 0
LABEL SLOWCLKEN
DEFAULT 0
DESCRIPTION Slow clock enable. Used for both the jack insert detect debounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled
Table 33 Timeout Clock Enable Control
MONO MIXER AND OUTPUT
The MONOOUT pin can drive a 16 or 32 headphone or a line output or be used as a DC reference for a headphone output (see Headphone Output section). It can be selected to drive out any combination of DAC, Bypass (output of input BOOST stage) and MIC2. The Bypass path has the option of 0dB or -10dB attenuation, selected by the MONOATTN register bit. This output is enabled by setting bit MONOEN.
REGISTER ADDRESS R40 Attenuation Control
BIT 1 2
LABEL SPKATTN MONOATTN 0 0
DEFAULT 0=off 1=-10dB 0=off 1=-10dB
DESCRIPTION
Table 34 Sidetone Attenuation Control
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REGISTER ADDRESS R56 Mono mixer control BIT 0 LABEL DAC2MONO DEFAULT 0 DESCRIPTION Output of DAC to mono mixer input 0 = not selected 1 = selected Bypass path (output of input boost stage) to mono mixer input 0 = non selected 1 = selected Output of MIC2 amplifier to mono mixer input: 0 = not selected 1 = selected 0=No mute 1=Output muted. During mute the mono output will output VMID which can be used as a DC reference for a headphone out. Attenuation control for bypass path (output of input boost stage) to mono mixer input 0 = 0dB 1 = -10dB
1
BYP2MONO
0
2
MIC2_2MONO
0
6
MONOMUTE
0
R40 Bypass path attenuation control
2
MONOATTN
0
Table 35 Mono Mixer Control
ENABLING THE OUTPUTS
Each analogue output of the WM8510 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All outputs are disabled by default. To save power, unused parts of the WM8510 should remain disabled. Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled (BUFIOEN=0), as this may cause pop noise (see "Power Management" and "Applications Information" sections).
REGISTER ADDRESS R1 Power management 1 R3 Power management 3
BIT 2 8 3 2 3 5 6 7
LABEL BUFIOEN BUFDCOPEN BIASEN SPKMIXEN MONOMIXEN SPKPEN SPKNEN MONOEN
DEFAULT 0 0 0 0 0 0 0 0
DESCRIPTION Unused input/output tie off buffer enable Output stage 1.5xAVDD/2 driver enable Analogue amplifiers bias enable Speaker Mixer enable Mono mixer enable SPKOUTP enable SPKOUTN enable MONOOUT enable
Note: All "Enable" bits are 1 = ON, 0 = OFF Table 36 Output Stages Power Management Control
UNUSED ANALOGUE INPUTS/OUTPUTS
Whenever an analogue input/output is disabled, it remains connected to a voltage source (either AVDD/2 or 1.5xAVDD/2 as appropriate) through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between the voltage buffer and the output pins can be controlled using the VROI control bit. The default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to about 30k.
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REGISTER ADDRESS R49 BIT 0 LABEL VROI DEFAULT 0
Production Data
DESCRIPTION VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1k 1: approx 30 k
Table 37 Disabled Outputs to VREF Resistance A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 21. This buffer can be enabled using the BUFIOEN register bit. If the SPKBOOST or MONOBOOST bits are set then the relevant outputs will be tied to the output of the DC level shift buffer at 1.5xAVDD/2 when disabled. Table 38 summarises the tie-off options for the speaker and mono output pins.
Figure 21 Unused Input/Output Pin Tie-off Buffers MONOEN/ SPKN/PEN 0 0 0 0 1 1 MONOBOOST/ SPKBOOST 0 0 1 1 0 1 VROI 0 1 0 1 X X OUTPUT CONFIGURATION 1k tieoff to AVDD/2 30k tieoff to AVDD/2 1k tieoff to 1.5xAVDD/2 30k tieoff to 1.5xAVDD/2 Output enabled (DC level=AVDD/2) Output enabled (DC level=1.5xAVDD/2)
Table 38 Unused Output Pin Tie-off Options
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OUTPUT SWITCH
When the device is configured with a 2-wire interface the CSB/GPIO pin can be used as a switch control input to automatically disable the speaker outputs and enable the mono output. For example when a line is plugged into a jack socket. In this mode, enabled by setting GPIOSEL=001, pin CSB/GPIO switches between mono and speaker outputs (e.g. when pin 12 is connected to a mechanical switch in the headphone socket to detect plug-in). The GPIOPOL bit reverses the polarity of the CSB/GPIO input pin. Note that the speaker outputs and the mono output must be enabled for this function to work (see Table 39). The CSB/GPIO pin has an internal de-bounce circuit when in this mode in order to prevent the output enables from toggling multiple times due to input glitches. This debounce circuit is clocked from a slow clock with period 221 x MCLK, enabled using the SLOWCLKEN register bit. GPIOPOL CSB/GPIO SPKNEN/ SPKPEN X X 0 1 X X 0 1 MONOEN SPEAKER ENABLED No No No Yes No No No Yes MONO OUTPUT ENABLED No Yes No No No Yes No No
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 X X 0 1 X X
Table 39 Output Switch Operation (GPIOSEL=001)
THERMAL SHUTDOWN
The speaker outputs can drive very large currents. To protect the WM8510 from overheating a thermal shutdown circuit is included. The thermal shutdown can be configured to produce an interrupt o when the device temperature reaches approximately 125 C. See the General Purpose Input/Output section for details.
REGISTER ADDRESS R49 Output control
BIT 1
LABEL TSDEN
DEFAULT 1
DESCRIPTION Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled
Table 40 Thermal Shutdown
SPEAKER OUTPUT
SPKOUTP/N can differentially drive a mono 8 Bridge Tied Load (BTL) speaker as shown below.
Figure 22 Speaker Output Connection
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HEADPHONE OUTPUT
Production Data
The speaker outputs can drive a 16 or 32 headphone load, either through DC blocking capacitors, or DC coupled without any capacitor. Headphone Output using DC Blocking Capacitors: DC Coupled Headphone Output:
Figure 23 Recommended Headphone Output Configurations When DC blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. Assuming a 16 load and C1, C2 = 220F: fc = 1 / 2 RLC1 = 1 / (2 x 16 x 220F) = 45 Hz In the DC coupled configuration, the headphone "ground" is connected to the MONOOUT pin. The MONOOUT pin can be configured as a DC output driver by setting the MONOMUTE register bit. The DC voltage on MONOOUT in this configuration is equal to the DC offset on the SPKOUTP and SPKOUTN pins therefore no DC blocking capacitors are required. This saves space and material cost in portable applications. It is recommended to connect the DC coupled outputs only to headphones, and not to the line input of another device. Although the built-in short circuit protection will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other device is grounded.
MONO OUTPUT
The mono output, can be used as a line output, a headphone output or as a pseudo ground for capless driving of loads by SPKOUT. Recommended external components are shown below.
Figure 24 Recommended Circuit for Line Output The DC blocking capacitors and the load resistance together determine the lower cut-off frequency, fc. Assuming a 10 k load and C1 = 1F: fc = 1 / 2 (RL+R1) C1 = 1 / (2 x 10.1k x 1F) = 16 Hz Increasing the capacitance lowers fc, improving the bass response. Smaller values of C1 will diminish the bass response. The function of R1 is to protect the line outputs from damage when used improperly.
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The audio interface has four pins: * * * * ADCDAT: ADC data output DACDAT: DAC data input FRAME: Data alignment clock BCLK: Bit clock, for synchronisation
DIGITAL AUDIO INTERFACES
The clock signals BCLK, and FRAME can be outputs when the WM8510 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Five different audio data formats are supported: * * * * Left justified Right justified I 2S DSP mode A
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8510 audio interface may be configured as either master or slave. As a master interface device the WM8510 generates BCLK and FRAME and thus controls sequencing of the data transfer on ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In slave mode (MS=0), the WM8510 responds with data to clocks it receives over the digital audio interfaces.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an FRAME transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each FRAME transition.
Figure 25 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a FRAME transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each FRAME transition.
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Figure 26 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a FRAME transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
Figure 27 I2S Audio Interface (assuming n-bit word length) In DSP/PCM mode, the left channel MSB is available on the 2nd (mode A) rising edge of BCLK (selectable by FRAMEP) following a rising edge of FRAME. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
Figure 28 DSP/PCM Mode Audio Interface (mode A) When using ADCLRSWAP = 1 or DACLRSWAP = 1 in DSP/PCM mode, the data will appear in the Right Phase of the FRAME, which will be 16/20/24/32 bits after the FRAME pulse.
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REGISTER ADDRESS R4 Audio interface control BIT 1 LABEL ADCLRSWAP DEFAULT 0 DESCRIPTION Controls whether ADC data appears in `right' or `left' phases of FRAME clock: 0=ADC data appear in `left' phase of FRAME 1=ADC data appears in `right' phase of FRAME Controls whether DAC data appears in `right' or `left' phases of FRAME clock: 0=DAC data appear in `left' phase of FRAME 1=DAC data appears in `right' phase of FRAME Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits (see note) Frame clock polarity 0=normal 1=inverted BCLK polarity 0=normal 1=inverted
2
DACLRSWAP
0
4:3
FMT
10
6:5
WL
10
7
FRAMEP
0
8
BCP
0
Table 41 Audio Interface Control
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised below. Each audio interface can be controlled individually. Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK, and FRAME are outputs. The frequency of BCLK and FRAME in master mode are controlled with BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses at the end of a frame if there is a non-integer ratio of BCLKs to FRAME clocks.
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REGISTER ADDRESS R6 Clock generation control BIT 0 MS LABEL DEFAULT 0
Production Data
DESCRIPTION Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8510 (MASTER) Configures the BCLK and FRAME output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output
4:2
BCLKDIV
000
7:5
MCLKDIV
010
8
CLKSEL
1
Table 42 Clock Control
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from the ADC audio interface is fed directly into the DAC data input.
COMPANDING
The WM8510 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively.
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REGISTER ADDRESS R5 Companding control BIT 0 LABEL LOOPBACK DEFAULT 0 DESCRIPTION Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. ADC companding 00=off 01=reserved 10=-law 11=A-law DAC companding 00=off 01=reserved 10=-law 11=A-law
2:1
ADC_COMP
0
4:3
DAC_COMP
0
Table 43 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) A-law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) F(x) = ( 1 + lnA|x|) / (1 + lnA) } for x } for 1/A 1/A x 1 -1 x 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB's of data. Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. This is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).
BIT7 SIGN
BIT[6:4] EXPONENT
BIT[3:0] MANTISSA
Table 44 8-bit Companded Word Composition
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u-law Companding
Production Data
1 120 100 Companded Output 80 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 29 u-Law Companding
A-law Companding
1 120 100 Companded Output 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 30 A-Law Companding
AUDIO SAMPLE RATES
The WM8510 sample rates for the ADC and the DAC are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate. If a sample rate that is not explicitly supported by the SR register settings is required then the closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay and hold times will scale appropriately.
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REGISTER ADDRESS R7 Additional control BIT 3:1 LABEL SR DEFAULT 000 DESCRIPTION Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved
Table 45 Sample Rate Control
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
The WM8510 has an on-chip phase-locked loop (PLL) circuit that can be used to: Generate master clocks for the WM8510 audio functions from another external clock, e.g. in telecoms applications. Generate and output (on pin CSB/GPIO) a clock for another part of the system that is derived from an existing audio master clock. Figure 31 shows the PLL and internal clocking arrangement on the WM8510. The PLL can be enabled or disabled by the PLLEN register bit. Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL.
REGISTER ADDRESS R1 Power management 1
BIT 5
LABEL PLLEN
DEFAULT 0 PLL enable 0=PLL off 1=PLL on
DESCRIPTION
Table 46 PLLEN Control Bit
Figure 31 PLL and Clock Select Circuit
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PLLN = int R PLLK = int (224 (R-PLLN)) EXAMPLE: MCLK=12MHz, required clock = 12.288MHz.
Production Data The PLL frequency ratio R = f2/f1 (see Figure 31) can be set using the register bits PLLK and PLLN:
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement. Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz. R = 98.304 / 12 = 8.192 PLLN = int R = 8 k = int ( 224 x (8.192 - 8)) = 3221225 = 3126E9h REGISTER ADDRESS R36 PLL N value 4 BIT LABEL PLLPRESCALE DEFAULT 0 DESCRIPTION 0 = MCLK input not divided (default) 1= Divide MCLK by 2 before input to PLL Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
3:0
PLLN
1000
R37 PLL K value 1 R38 PLL K Value 2 R39 PLL K Value 3
5:0 8:0 8:0
PLLK [23:18] PLLK [17:9] PLLK [8:0]
0Ch 093h 0E9h
Table 47 PLL Frequency Ratio Control The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown in Table 48. MCLK (MHz) (F1) 12 12 13 13 14.4 14.4 19.2 19.2 19.68 19.68 19.8 19.8 24 24 26 26 27 27 DESIRED OUTPUT (MHz) 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 F2 (MHz) 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 PRESCALE DIVIDE 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 POSTSCALE DIVIDE 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 R N (Hex) 7 8 6 7 6 6 9 A 9 9 9 9 7 8 6 7 6 7 K (Hex) 86C226 3126E8 F28BD4 8FD525 45A1CA D3A06E 6872AF 3D70A3 2DB492 FD809F 1F76F7 EE009E 86C226 3126E8 F28BD4 8FD525 BOAC93 482296
7.5264 8.192 6.947446 7.561846 6.272 6.826667 9.408 10.24 9.178537 9.990243 9.122909 9.929697 7.5264 8.192 6.947446 7.561846 6.690133 7.281778
Table 48 PLL Frequency Examples
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GENERAL PURPOSE INPUT/OUTPUT
The CSB/GPIO pin can be configured to perform a variety of useful tasks by setting the GPIOSEL register bits. The GPIO is only available in 2 wire mode. Note that SLOWCLKEN must be enabled when using the Jack Detect function REGISTER ADDRESS R8 GPIO control BIT 2:0 LABEL GPIOSEL DEFAULT 000 DESCRIPTION CSB/GPIO pin function select: 000=CSB input 001= Jack insert detect 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=Reserved 111=Reserved GPIO Polarity invert 0=Non inverted 1=Inverted PLL Output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4
3
GPIOPOL
0
5:4
OPCLKDIV
00
Table 49 CSB/GPIO Control
CONTROL INTERFACE
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin determines the 2 or 3 wire mode as shown in Table 50. The WM8510 is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each control register. MODE Low High INTERFACE FORMAT 2 wire 3 wire
Table 50 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO latches in a complete control word consisting of the last 16 bits.
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Figure 32 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8510 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the WM8510). The WM8510 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8510, then the WM8510 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is `1' when operating in write only mode, the WM8510 returns to the idle condition and wait for a new start condition and valid address. During a write, once the WM8510 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8510 register address plus the first bit of register data). The WM8510 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8510 acknowledges again by pulling SDIN low. Transfers are complete when there is a low to high transition on SDIN while SCLK is high. After a complete sequence the WM8510 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
SDIN
DEVICE ADDRESS (7 BITS)
RD / WR BIT
ACK (LOW)
CONTROL BYTE 1 (BITS 15 TO 8)
ACK (LOW)
CONTROL BYTE 1 (BITS 7 TO 0)
ACK (LOW)
SCLK
START
register address and 1st register data bit
remaining 8 bits of register data
STOP
Figure 33 2-Wire Serial Control Interface In 2-wire mode the WM8510 has a fixed device address, 0011010.
RESETTING THE CHIP
The WM8510 can be reset by performing a write of any value to the software reset register (address 0 hex). This will cause all register values to be reset to their default values. In addition to this there is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the device is powered up.
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POWER SUPPLIES
The WM8510 can use up to four separate power supplies: AVDD and AGND: Analogue supply, powers all analogue functions except the speaker output and mono output drivers. AVDD can range from 2.5V to 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphone). A large AVDD slightly improves audio quality. SPKVDD and SPKGND: Headphone and Speaker supplies, power the speaker and mono output drivers. SPKVDD can range from 2.5V to 5.5V. SPKVDD can be tied to AVDD, but it requires separate layout and decoupling capacitors to curb harmonic distortion. With a larger SPKVDD, louder headphone and speaker outputs can be achieved with lower distortion. If SPKVDD is lower than AVDD (or 1.5 x AVDD for BOOST mode), the output signal may be clipped. DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces. DCVDD can range from 1.71V to 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DCVDD should be greater than or equal to 1.9V when using the PLL. DBVDD can range from 1.71V to 3.6V. DBVDD return path is through DGND. It is possible to use the same supply voltage for all four supplies. However, digital and analogue supplies should be routed and decoupled separately on the PCB to keep digital switching noise out of the analogue signal paths. Note: DCVDD should be greater than or equal to 1.9V when using the PLL.
RECOMMENDED POWER UP/DOWN SEQUENCE
In order to minimise output pop and click noise, it is recommended that the WM8510 device is powered up and down using one of the following sequences: Power Up When NOT Using the Output 1.5x Boost Stage: 1. 2. Turn on external power supplies. Wait for supply voltage to settle. Set BIASEN = 1, BUFIOEN = 1 and also the VMIDSEL[1:0] bits in the Power Management 1 register. * Notes 1 and 2. Wait for the VMID supply to settle. * Note 2. Enable DAC by setting DACEN = 1. Enable mixers as required. Enable output stages as required. Unmute DAC by setting DACMU = 0.
3. 4. 5. 6. 7.
Power Up When Using the Output 1.5x Boost Stage: 1. 2. 3. Turn on external power supplies. Wait for supply voltage to settle. Enable 1.5x output boost. Set MONOBOOST = 1 and SPKBOOST = 1 as required. Set BIASEN = 1, BUFIOEN = 1, BUFDCOPEN = 1 and also the VMIDSEL[1:0] bits in the Power Management 1 register. * Notes 1 and 2. Wait for the VMID supply to settle. * Note 2. Enable DAC by setting DACEN = 1. Enable mixers as required. Enable output stages as required. Unmute DAC by setting DACMU = 0.
4. 5. 6. 7. 8.
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Power Down (all cases): 1. 2. 3. 4. Soft mute DAC by setting DACMU = 1. Disable power management register 1 by setting R1[8:0]=0x000 Disable all other output stages. Turn off external power supplies.
Production Data
Notes: 1. This step enables the internal device bias buffer and the VMID buffer for unassigned inputs/outputs. This will provide a startup reference voltage for all inputs and outputs. This will cause the inputs and outputs to ramp towards VMID (NOT using output 1.5x boost) or 1.5 x (AVDD/2) (using output 1.5x boost) in a way that is controlled and predictable (see note 2). Choose the value of the VMIDSEL bits based on the startup time (VMIDSEL=10 for slowest startup, VMIDSEL=11 for fastest startup). Startup time is defined by the value of the VMIDSEL bits (the reference impedance) and the external decoupling capacitor on VMID.
2.
In addition to the power on sequence, it is recommended that the zero cross functions are used when changing the volume in the PGAs to avoid any audible pops or clicks.
Vpor_on Vpora
Power Supply
DGND
Vpor_off
POR
No Power POR Undefined POR
Device Ready Internal POR active DNC
I2S Clocks
DNC
ADC Internal State
tadcint
Power down Init Normal Operation PD Init
tadcint
Normal Operation Power down
tmidrail_on
(Note 1)
tmidrail_off
(Note 2)
Analogue Inputs ADCDAT pin
(Note 3)
AVDD/2 GD GD GD GD
ADCEN bit INPPGAEN bit VMIDSEL/ BIASEN bits
(Note 4)
ADC enabled
ADC off
ADC enabled
INPPGA enabled
VMID enabled
Figure 34 ADC Power Up and Down Sequence (not to scale)
SYMBOL tmidrail_on tmidrail_off tadcint
MIN
TYPICAL 500 >10 2/fs
MAX
UNIT ms s n/fs
Table 51 Typical POR Operation (typical values, not tested)
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WM8510
The analogue input pin charge time, tmidrail_on, is determined by the VMID pin charge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The analogue input pin discharge time, tmidrail_off, is determined by the analogue input coupling capacitor discharge time. The time, tmidrail_off, is measured using a 1F capacitor on the analogue input but will vary dependent upon the value of input coupling capacitor. While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system noise but no significant digital output will be present. The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for normal ADC operation. ADCDAT data output delay from power up - with power supplies starting from 0V - is determined primarily by the VMID charge time. ADC initialisation and power management bits may be set immediately after POR is released; VMID charge time will be significantly longer and will dictate when the device is stabilised for analogue input. ADCDAT data output delay at power up from device standby (power supplies already applied) is determined by ADC initialisation time, 2/fs.
2.
3.
4.
5.
6.
Figure 35 DAC Power Up and Down Sequence (not to scale)
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SYMBOL tline_midrail_on tline_midrail_off thp_midrail_on thp__midrail_off tdacint MIN TYPICAL 500 1 500 6 2/fs MAX UNIT ms s ms s n/fs
Production Data
Table 52 Typical POR Operation (typical values, not tested) Notes: 1. The lineout charge time, tline_midrail_on, is mainly determined by the VMID pin charge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The values above were measured using a 4.7F capacitor. It is not advisable to allow DACDAT data input during initialisation of the DAC. If the DAC data value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue outputs. The same is also true if the DACDAT is removed at a non-zero value, and no mute function has been applied to the signal beforehand. The lineout discharge time, tline_midrail_off, is dependent upon the value of the lineout coupling capacitor and the leakage resistance path to ground. The values above were measured using a 10F output capacitor. The headphone charge time, thp_midrail_on, is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The values above were measured using a 4.7F VMID decoupling capacitor. The headphone discharge time, thp_midrail_off, is dependent upon the value of the headphone coupling capacitor and the leakage resistance path to ground. The values above were measured using a 100F capacitor.
2.
3.
4.
5.
The VMIDSEL and BIASEN bits must be set to enable analogue output midrail voltage and for normal DAC operation.
POWER MANAGEMENT
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. REGISTER ADDRESS R10 DAC control R14 ADC control 3 BIT LABEL DACOSR128 DEFAULT 0 DESCRIPTION DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR)
3
ADCOSR128
0
Table 53 ADC and DAC Oversampling Rate Selection
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VMID
The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the startup time of the VMID circuit. REGISTER ADDRESS R1 Power management 1 BIT 1:0 LABEL VMIDSEL DEFAULT 00 DESCRIPTION Reference string impedance to VMID pin (determines startup time): 00=off (open circuit) 01=75k 10=300k 11=2.5k (for fastest startup)
Table 54 VMID Impedance Control
BIASEN
REGISTER ADDRESS R1 Power management 1 BIT 3 LABEL BIASEN DEFAULT 0 DESCRIPTION Analogue amplifier bias control 0=Disabled 1=Enabled
Table 55 BIASEN Control
ESTIMATED SUPPLY CURRENTS
When either the DAC or ADC are enabled it is estimated that approximately 4mA will be drawn from DCVDD when DCVDD=1.8V and fs=48kHz (This will be lower at lower sample rates). When the PLL is enabled an additional 700 microamps will be drawn from DCVDD.
Table 45 shows the estimated 3.3V AVDD current drawn by various circuits, by register bit. REGISTER BIT BUFDCOPEN MONOEN PLLEN MICBEN BIASEN BUFIOEN VMIDSEL BOOSTEN INPPGAEN ADCEN MONOEN SPKPEN SPKNEN MONOMIXEN SPKMIXEN DACEN 0.1 0.2 1.4 (with clocks applied) 0.5 0.3 0.1 10K=>0.3, less than 0.1 for 100k/500k 0.2 0.2 x64 (ADCOSR=0)=>2.6, x128 (ADCOSR=1)=>4.9 0.2 1mA from SPKVDD + 0.2mA from AVDD in 5V mode 1mA from SPKVDD + 0.2mA from AVDD in 5V mode 0.2 0.2 x64 (DACOSR=0)=>1.8, x128(DACOSR=1)=>1.9 AVDD CURRENT (MILLIAMPS)
Table 56 AVDD Supply Current
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POWER SAVING
Production Data
For minimum power consumption in standby mode, VMIDSEL should not be set to default. Instead, the following sequence of writes should be implemented: 1. 2. 3. 4. 5. R10[6] = 1 (DACMU=1). R1 = 0x00. R2 = 0x00. R3 = 0x00 R1 = 0x02 (VMIDSEL[1:0] = 10).
After reset, all register values are set to default. In order to achieve minimum power consumption, the following sequence of writes should be implemented. 1. 2. 3. 4. R10[6] = 1 (DACMU=1). R1 = 0x00. R0 = 0xFF. R1 = 0x02 (VMIDSEL[1:0] = 10).
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REGISTER MAP
ADDR B[15:9]
DEC
HEX
REGISTER NAME Software Reset Power manage't 1 Power manage't 2 Power manage't 3 Audio Interface Companding ctrl Clock Gen ctrl Additional ctrl GPIO Stuff DAC Control DAC digital Vol ADC Control ADC Digital Vol DAC Limiter 1 DAC Limiter 2 Notch Filter 1 Notch Filter 2 Notch Filter 3 Notch Filter 4 ALC control 1 ALC control 2 ALC control 3 Noise Gate PLL N PLL K 1 PLL K 2 PLL K 3 Attenuation ctrl Input ctrl INP PGA gain ctrl ADC Boost ctrl Output ctrl SPK mixer ctrl SPK volume ctrl MONO mixer ctrl
B8
B7
B6
B5
B4
B3
B2
B1
B0
DEF'T VAL (HEX)
0 1 2 3 4 5 6 7 8 10 11 14 15 24 25 27 28 29 30 32 33 34 35 36 37 38 39 40 44 45 47 49 50 54 56
00 01 02 03 04 05 06 07 08 0A 0B 0E 0F 18 19 1B 1C 1D 1E 20 21 22 23 24 25 26 27 28 2C 2D 2F 31 32 36 38
Software reset BUFDCOP EN 0 0 BCP 0 CLKSEL 0 0 0 0 HPFEN 0 LIMEN 0 NFU NFU NFU NFU ALCSEL ALCZC ALCMODE 0 0 0 0 0 0 0 0 0 PLLK[17:9] PLLK[8:0] 0 MBVSEL 0 PGABOOST 0 0 0 0 0 0 INPPGAZC 0 0 0 SPKZC 0 0 0 SPKMUTE MONO MUTE 0 0 0 0 0 INPPGA MUTE MICP2BOOSTVOL 0 MIC2_2SP K 0 0 0 0 0 0 0 MIC2MOD E MONOATTN SPKATTN MIC2_2 INPPGA MICN2 INPPGA 0 MICP2 INPPGA 0 NFEN 0 0 0 0 0 ALCHLD ALCDCY 0 0 0 PLL_PRE SCALE PLLK[23:18] NGEN ALCMAX LIMDCY LIMLVL NFA0[13:7] NFA0[6:0] NFA1[13:7] NFA1[6:0] ALCMIN ALCLVL ALCATK NGTH PLLN[3:0] HPFAPP HPFCUT 0 0 0 0 0 MONOEN FRAMEP 0 0 MCLKDIV 0 0 DACMU 0 0 GPIOPOL DACOSR 128 DACVOL ADCOSR 128 ADCVOL LIMATK LIMBOOST 0 0 ADCPOL AMUTE MIC2EN 0 SPKNEN WL 0 PLLEN 0 SPKPEN MICBEN BOOSTEN 0 FMT DAC_COMP BCLKDIV SR GPIOSEL 0 DACPOL BIASEN 0 MONO MIXEN BUFIOEN INPPGAEN SPK MIXEN 0 0 VMIDSEL ADCEN DACEN 0 LOOPBACK MS SLOWCLK EN 000 000 000 050 000 140 000 000 000 0FF 100 0FF 032 000 000 000 000 000 038 00B 032 000 008 00C 093 0E9 000 003 010 MIC2_2BOOSTVOL SPK BOOST 0 SPKVOL MIC2_2 MONO BYP2 MONO DAC2 MONO TSDEN VROI 100 002 000 039 000
DACLRSW ADCLRSW AP AP ADC_COMP 0
OPCLKDIV DEEMPH
INPPGAVOL 0 MONO BOOST 0
BYP2SPK DAC2SPK
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REGISTER BITS BY ADDRESS
Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default.
REGISTER ADDRESS
Production Data
BIT [8:0] 8
LABEL RESET BUFDCOPEN
DEFAULT N/A 0 Software reset
DESCRIPTION
REFER TO Resetting the Chip Analogue Outputs
0 (00h) 1 (01h)
Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. 0=Buffer disabled 1=Buffer enabled (required for 1.5x gain boost) Reserved MIC2 input buffer enable 0 = OFF 1 = ON PLL enable 0=PLL off 1=PLL on Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Analogue amplifier bias control 0=Disabled 1=Enabled Unused input/output tie off buffer enable 0=Disabled 1=Enabled Reference string impedance to VMID pin: 00=off (open circuit) 01=75k 10=300k 11=2.5k Reserved Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Reserved Input microphone PGA enable 0 = disabled 1 = enabled Reserved ADC Enable Control 0 = ADC disabled 1 = ADC enabled Reserved MONOOUT enable 0 = disabled 1 = enabled SPKOUTN enable 0 = disabled 1 = enabled
7 6 MIC2EN
0 0
MIC Inputs
5
PLLEN
0
Master Clock and Phase Locked Loop (PLL) Microphone Biasing Circuit Power Management Enabling the Outputs Power Management
4
MICBEN
0
3
BIASEN
0
2
BUFIOEN
0
1:0
VMIDSEL
00
2 (02h)
8:5 4 BOOSTEN
0000 0
Input Boost
3 2 INPPGAEN
0 0
Input Signal Path
1 0 ADCEN
0 0
Analogue to Digital Converter (ADC)
3 (03h)
8 7 MONOEN
0 0
Analogue Outputs Analogue Outputs
6
SPKNEN
0
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REGISTER ADDRESS
WM8510
BIT 5 LABEL SPKPEN DEFAULT 0 SPKOUTP enable 0 = disabled 1 = enabled Reserved Mono Mixer Enable 0 = disabled 1 = enabled Speaker Mixer Enable 0 = disabled 1 = enabled Reserved DAC enable 0 = DAC disabled 1 = DAC enabled BCLK polarity 0=normal 1=inverted Frame clock polarity 0=normal 1=inverted Analogue Outputs Digital Audio Interfaces Digital Audio Interfaces Analogue Outputs Analogue Outputs DESCRIPTION REFER TO Analogue Outputs
4 3 MONOMIXEN
0 0
2
SPKMIXEN
0
1 0 DACEN
0 0
4 (04h)
8
BCP
0
7
FRAMEP
0
6:5
WL
10
Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode Controls whether DAC data appears in `right' or `left' phases of FRAME clock: 0=DAC data appear in `left' phase of FRAME 1=DAC data appears in `right' phase of FRAME Controls whether ADC data appears in `right' or `left' phases of FRAME clock: 0=ADC data appear in `left' phase of FRAME 1=ADC data appears in `right' phase of FRAME Reserved Reserved DAC companding 00=off 01=reserved 10=-law 11=A-law ADC companding 00=off 01=reserved 10=-law 11=A-law
Digital Audio Interfaces
4:3
FMT
10
Digital Audio Interfaces
2
DACLRSWAP
0
Digital Audio Interfaces
1
ADCLRSWAP
0
Digital Audio Interfaces
0 5 (05h) 8:5 4:3 DAC_COMP
0 0000 00
Digital Audio Interfaces
2:1
ADC_COMP
00
Digital Audio Interfaces
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REGISTER ADDRESS
Production Data BIT 0 LABEL LOOPBACK DEFAULT 0 DESCRIPTION Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Configures the BCLK and FRAME output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Reserved Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8510 (MASTER) Reserved Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved Slow clock enable. Used for both the jack insert detect debounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled Reserved PLL Output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 General Purpose Input Output Audio Sample Rates Digital Audio Interfaces REFER TO Digital Audio Interfaces
6 (06h)
8
CLKSEL
1
Digital Audio Interfaces
7:5
MCLKDIV
010
Digital Audio Interfaces
4:2
BCLKDIV
000
Digital Audio Interfaces
1 0 MS
0 0
7 (07h)
8:4 3:1 SR
00000 000
0
SLOWCLKEN
0
Audio Sample Rates
8 (08h)
8:6 5:4 OPCLKDIV
000 00
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REGISTER ADDRESS
WM8510
BIT 3 LABEL GPIOPOL DEFAULT 0 DESCRIPTION GPIO Polarity invert 0=Non inverted 1=Inverted CSB/GPIO pin function select: 000=CSB input 001= Jack insert detect 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=Reserved 111=Reserved Reserved 00 DACMU 0 Reserved DAC soft mute enable 0 = DACMU disabled 1 = DACMU enabled De-Emphasis Control 00 = No de-emphasis 01 = 32kHz sample rate 10 = 44.1kHz sample rate 11 = 48kHz sample rate DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) DAC auto mute enable 0 = auto mute disabled 1 = auto mute enabled Reserved DAC Polarity Invert 0 = No inversion 1 = DAC output inverted Reserved DAC Digital Volume Control 0000 0000 = Unused 0000 0001 = -127dB = mute 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Reserved Reserved HPFEN 1 High Pass Filter Enable 0=disabled 1=enabled Select audio mode or application mode 0=Audio mode (1st order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) Application mode cut-off frequency See Table 11 details. ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Power Management Output Signal Path Output Signal Path Output Signal Path Output Signal Path REFER TO General Purpose Input Output General Purpose Input Output
2:0
GPIOSEL
000
9 (09h) 10 (0Ah)
8:0 8:7 6
5:4
DEEMPH
00
3
DACOSR128
0
Power Management Output Signal Path
2
AMUTE
0
1 0 DACPOL
0 0
11 (0Bh)
8 7:0 DACVOL
0 11111111
12 (0Ch) 13 (0Dh) 14 (0Eh)
8:0 8:0 8
7
HPFAPP
0
6:4
HPFCUT
000
3
ADCOSR128
0
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REGISTER ADDRESS
Production Data BIT 2:1 0 ADCPOL LABEL DEFAULT 00 0 Reserved ADC Polarity 0=normal 1=inverted Reserved ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Enable the DAC digital limiter: 0=disabled 1=enabled DAC Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s DAC Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms Reserved DAC Limiter Programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB Output Signal Path Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) DESCRIPTION REFER TO
15 (0Fh)
8 7:0 ADCVOL
0 11111111
24 (18h)
8
LIMEN
0
Output Signal Path Output Signal Path
7:4
LIMDCY
0011
3:0
LIMATK
0010
Output Signal Path
25 (19h)
8:7 6:4 LIMLVL
00 000
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REGISTER ADDRESS
WM8510
BIT 3:0 LABEL LIMBOOST DEFAULT 0000 DESCRIPTION DAC Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000=0dB 0001=+1dB 0010=+2dB ... (1dB steps) 1011=+11dB 1100=+12dB 1101 to 1111=reserved Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch filter enable: 0=Disabled 1=Enabled Notch Filter a0 coefficient, bits [13:7] REFER TO Output Signal Path
27 (1Bh)
8
NFU
0
Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Input Limiter / Automatic Level Control (ALC)
7
NFEN
0
6:0
NFA0[13:7]
0000000
28 (1Ch)
8
NFU
0
Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Reserved Notch Filter a0 coefficient, bits [6:0]
7 6:0 NFA0[6:0]
0 0000000
29 (1Dh)
8
NFU
0
Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Reserved Notch Filter a1 coefficient, bits [13:7]
7 6:0 NFA1[13:7]
0 0000000
30 (1Eh)
8
NFU
0
Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Reserved Notch Filter a1 coefficient, bits [6:0]
7 6:0 NFA1[6:0]
0 0000000
32 (20h)
8
ALCSEL
0
ALC function select: 0=ALC off (PGA gain set by INPPGAVOL register bits) 1=ALC on (ALC controls PGA gain) Reserved Set Maximum Gain of PGA when using ALC: 111=+35.25dB 110=+29.25dB 101=+23.25dB 100=+17.25dB 011=+11.25dB 010=+5.25dB 001=-0.75dB 000=-6.75dB
7:6 5:3 ALCMAX 111
Input Limiter / Automatic Level Control (ALC)
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REGISTER ADDRESS
Production Data BIT 2:0 LABEL ALCMIN DEFAULT 000 DESCRIPTION Set minimum gain of PGA when using ALC: 000=-12dB 001=-6dB 010=0dB 011=+6dB 100=+12dB 101=+18dB 110=+24dB 111=+30dB ALC zero cross detection. 0 = disabled (recommended) 1 = enabled It is recommended that zero cross is not used in conjunction with the ALC or Limiter functions ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ... (time doubles with every step) 1111 = 43.691s ALC target - sets signal level at ADC input 0000 = -28.5dB FS 0001 = -27.0dB FS ... (1.5dB steps) 1110 = -7.5dB FS 1111 = -6dB FS Determines the ALC mode of operation: 0=ALC mode 1=Limiter mode. Decay (gain ramp-up) time (ALCMODE =0) Per step 0000 0001 0010 1010 or higher 0011 410us 820us 1.64ms 420ms Per 6dB 3.38ms 6.6ms 13.1ms 3.36s 90% of range 23.6ms 47.2ms 94.5 24.2s REFER TO Input Limiter / Automatic Level Control (ALC)
33 (21h)
8
ALCZC
0
Input Limiter / Automatic Level Control (ALC)
7:4
ALCHLD
000
Input Limiter / Automatic Level Control (ALC)
3:0
ALCLVL
1011
Input Limiter / Automatic Level Control (ALC)
34 (22h)
8
ALCMODE
0
Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC)
7:4
ALCDCY
0011
... (time doubles with every step)
Decay (gain ramp-up) time (ALCMODE =1) Per step 0000 0001 0010 1010 90.8us 182us 363us 93ms Per 6dB 726us 1.45ms 2.91ms 744ms 90% of range 5.23ms 10.5ms 20.9ms 5.36s Input Limiter / Automatic Level Control (ALC)
... (time doubles with every step) 3:0 ALCATK 0010 ALC attack (gain ramp-down) time (ALCMODE = 0) Per step 0000 0001 0010 104us 208us 416us Per 6dB 832us 1.664ms 3.33ms 90% of range 6ms 12ms 24ms PD Rev 4.1 December 2006 70
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REGISTER ADDRESS
WM8510
BIT LABEL DEFAULT DESCRIPTION ... (time doubles with every step) 1010 or higher 0010 106ms 852ms 6.18s REFER TO
ALC attack (gain ramp-down) time (ALCMODE = 1) Per step 0000 0001 0010 1010 22.7us 45.4us 90.8us 23.2ms Per 6dB 182.4us 363us 726us 186ms 90% of range 1.31ms 2.62ms 5.23ms 1.34s Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC)
... (time doubles with every step) 35 (23h) 8:4 3 NGEN 00000 0 Reserved ALC Noise gate function enable 1 = enable 0 = disable ALC Noise gate threshold: 000=-39dB 001=-45dB 010=-51db ... (6dB steps) 111=-81dB Reserved 0 = MCLK input not divided (default) 1 = Divide MCLK by 2 before input PLL Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Analogue Outputs
2:0
NGTH
000
36 (24h)
8:5 4 PLLPRESCALE
0000 0
3:0
PLLN[3:0]
1000
Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13.
37 (25h)
8:6 5:0 PLLK[23:18]
000 001100
Reserved Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
38 (26h)
8:0
PLLK[17:9]
01001001 1
Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
39 (27h)
8:0
PLLK[8:0]
01110100 1
Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
40 (28h)
8:3 2 MONOATTN
000000 0
Reserved Attenuation control for bypass path (output of input boost stage) to mono mixer input 0 = 0dB 1 = -10dB Attenuation control for bypass path (output of input boost stage) to speaker mixer input 0 = 0dB 1 = -10dB Reserved
1
SPKATTN
0
Analogue Outputs
0
0
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REGISTER ADDRESS
Production Data BIT 8 LABEL MBVSEL DEFAULT 0 DESCRIPTION Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.75 * AVDD Reserved Auxiliary Input Mode 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed) Select AUX amplifier output as input PGA signal source. 0=AUX not connected to input PGA 1=AUX connected to input PGA amplifier negative terminal. Connect MICN to input PGA negative terminal. 0=MICN not connected to input PGA 1=MICN connected to input PGA amplifier negative terminal. Connect input PGA amplifier positive terminal to MICP or VMID. 0 = input PGA amplifier positive terminal connected to VMID 1 = input PGA amplifier positive terminal connected to MICP through variable resistor string Reserved Input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB Input Boost 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Reserved Controls the MICP pin to the input boost stage (NB, when using this path set MICP2INPPGA=0): 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Reserved Input Signal Path Input Signal Path Input Signal Path Input Signal Path REFER TO Input Signal Path
44 (2Ch)
7:4 3 MIC2MODE
0000 0
2
MIC2_2INPP GA
0
1
MICN2INPPGA
1
Input Signal Path
0
MICP2INPPGA
1
Input Signal Path
45 (2Dh)
8 7 INPPGAZC
0 0
6
INPPGAMUTE
0
Input Signal Path
5:0
INPPGAVOL
010000
Input Signal Path
47 (2Fh)
8
PGABOOST
1
Input Signal Path
7 6:4 MICP2BOOST VOL
0 000
3
0
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REGISTER ADDRESS
WM8510
BIT 2:0 LABEL MIC2_2BOOST VOL DEFAULT 000 DESCRIPTION Controls the auxilliary amplifer to the input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Reserved Mono output boost stage control (see Table 30 for details) 0=No boost (output is inverting buffer) 1=1.5x gain boost Speaker output boost stage control (see Table 30 for details) 0=No boost (outputs are inverting buffers) 1 = 1.5x gain boost Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1k 1: approx 30 k Reserved Output of auxiliary amplifier to speaker mixer input 0 = not selected 1 = selected Reserved Bypass path (output of input boost stage) to speaker mixer input 0 = not selected 1 = selected Output of DAC to speaker mixer input 0 = not selected 1 = selected Speaker Volume control zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Speaker output mute enable 0=Speaker output enabled 1=Speaker output muted (VMIDOP) Speaker Volume Adjust 111111 = +6dB 111110 = +5dB ... (1.0 dB steps) 111001=0dB ... 000000=-57dB Reserved Analogue Outputs Analogue Outputs Analogue Outputs REFER TO Input Signal Path
49 (31h)
8:4 3 MONOBOOST
00000 0
2
SPKBOOST
0
Analogue Outputs
1
TSDEN
1
Output Switch
0
VROI
0
Analogue Outputs
50 (32h)
8:6 5 MIC2_2SPK
000 0
4:2 1 BYP2SPK
000 0
0
DAC2SPK
0
Analogue Outputs
54 (36h)
8 7 SPKZC 0 Analogue Outputs Analogue Outputs Analogue Outputs
6
SPKMUTE
0
5:0
SPKVOL
111001
56 (38h)
8:7
0
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WM8510
REGISTER ADDRESS
Production Data BIT 6 LABEL MONOMUTE DEFAULT 0 DESCRIPTION MONOOUT Mute Control 0=No mute 1=Output muted. During mute the mono output will output VMID which can be used as a DC reference for a headphone out. Reserved Output of Auxillary amplifier to mono mixer input: 0 = not selected 1 = selected Bypass path (output of input boost stage) to mono mixer input 0 = non selected 1 = selected Output of DAC to mono mixer input 0 = not selected 1 = selected Analogue Outputs Analogue Outputs REFER TO Analogue Outputs
5:3 2 MIC2_2MONO
0 0
1
BYP2MONO
0
0
DAC2MONO
0
Analogue Outputs
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WM8510
DIGITAL FILTER CHARACTERISTICS
PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay3 ADC High Pass Filter High Pass Filter Corner Frequency -3dB -0.5dB -0.1dB DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay3 Table 57 Digital Filter Characteristics f > 0.546fs 0.546fs -55 29/fs dB +/- 0.035dB -6dB 0 0.5fs +/-0.035 dB 0.454fs 3.7 10.4 21.6 Hz f > 0.546fs 0.546fs -60 21/fs dB +/- 0.025dB -6dB 0 0.5fs +/- 0.025 dB 0.454fs TEST CONDITIONS MIN TYP MAX UNIT
TERMINOLOGY
1. 2. 3. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple - any variation of the frequency response in the pass-band region Note that this delay applies only to the filters and does not include additional delays through other digital circuits.
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WM8510
DAC FILTER RESPONSES
0.2
0
Production Data
0.15
-20 Response (dB) -40 -60 -80 -100
0.1 Response (dB)
0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
0.05 0 -0.05 -0.1 -0.15
-120
-0.2 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5
Figure 36 DAC Digital Filter Frequency Response
Figure 37 DAC Digital Filter Ripple
ADC FILTER RESPONSES
0.2
0 -20 Response (dB)
Response (dB)
0.15 0.1 0.05 0 -0.05 -0.1
-40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.15 -0.2 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5
Figure 38 ADC Digital Filter Frequency Response
Figure 39 ADC Digital Filter Ripple
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WM8510
DE-EMPHASIS FILTER RESPONSES
0 -1 -2 -3 Response (dB) -4 -5 -6 -7 -8 -9 -10 0 2000 4000 6000 8000 10000 12000 14000 16000 Frequency (Hz)
0.30 0.25 0.20 Response (dB) 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 0 2000 4000 6000 8000 10000 12000 14000 16000 Frequency (Hz)
Figure 40 De-emphasis Frequency Response (32kHz)
Figure 41 De-emphasis Error (32kHz)
0 -1 -2 -3 Response (dB) -4 -5 -6 -7 -8 -9 -10 0 5000 10000 Frequency (Hz) 15000 20000
0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 0 5000 10000 Frequency (Hz) 15000 20000
Figure 42 De-emphasis Frequency Response (44.1kHz)
Figure 43 De-emphasis Error (44.1kHz)
0 -1 -2 -3 Response (dB) -4 -5 -6 -7 -8 -9 -10 0 5000 10000 Frequency (Hz) 15000 20000
Response (dB)
0.10 0.08 0.06 0.04 Response (dB) 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 5000 10000 Frequency (Hz) 15000 20000
Figure 44 De-emphasis Frequency Response (48kHz)
Figure 45 De-emphasis Error (48kHz)
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WM8510
HIGHPASS FILTER
Production Data
The WM8510 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1st order IIR with a cut-off of around 3.7Hz. In applications mode the filter is a 2nd order high pass filter with a selectable cut-off frequency.
5 0 -5 -10 Response (dB) -15 -20 -25 -30 -35 -40 0 5 10 15 20 25 30 35 40 45 Frequency (Hz)
Figure 46 ADC Highpass Filter Response, HPFAPP=0
10 0 -10
10 0 -10 -20
Response (dB)
-20 -30 -40
Response (dB)
-30 -40 -50 -60
-50 -60 0 200 400 600 Frequency (Hz) 800 1000 1200
-70 -80 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 47 ADC Highpass Filter Responses (48kHz), HPFAPP=1, all cut-off settings shown.
Figure 48 ADC Highpass Filter Responses (24kHz), HPFAPP=1, all cut-off settings shown.
10 0 -10 -20 Response (dB) -30 -40 -50 -60 -70 -80 -90 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 49 ADC Highpass Filter Responses (12kHz), HPFAPP=1, all cut-off settings shown.
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WM8510
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 50 Recommended External Components
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WM8510 PACKAGE DIAGRAM
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)
Production Data
DM007.E
b
28
e
15
E1
E
1
D
14
GAUGE PLANE
c A A2 A1
L
0.25
L1
-C0.10 C
SEATING PLANE
Symbols A A1 A2 b c D e E E1 L L1 REF: MIN ----0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.55 0
o
Dimensions (mm) NOM --------1.75 0.30 ----10.20 0.65 BSC 7.80 5.30 0.75 1.25 REF o 4 JEDEC.95, MO-150
MAX 2.0 0.25 1.85 0.38 0.25 10.50 8.20 5.60 0.95 8
o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8510
IMPORTANT NOTICE
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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